Case Study - Networking Systems Company (Turn-key Project)

 

Projects

• Design Highlights
• Xilinx Virtex4 FPGA for 10G Packet Processor
• 200 MHz core clock
• Activity
• RTL Design of parser, classifier, hashing, flow processor, stats, messaging
• Xilinx FPGA Implementation
• Functional Verification infrastructure of FPGA using Verilog
• Tools
• Synplicity – Synplify; Xilinx - ISE
• Cadence/Synopsys – NCVerilog/VCS
• Team Size
• Three engineers, 11 mo duration