- ASIC Verification test bench architecture for complex networking chip for virtualization servers.
- ASIC Verification for complex processor chipset using SystemVerilog UVM.
- ASIC/SoC Verification test bench architecture with SystemVerilog UVM environment for complex networking chip.
- FPGA RTL Design, Bring-up, and Characterization for DDR3 memory controller design.
- ASIC Verification for complex networking chip for virtualization servers using C, C++, Vera.
- Xilinx Virtex RTL Optimization for complex communications chip.
- ASIC physical design using mixed Cadence / Synopsys flow for Place & Route, STA, Synthesis, and Timing.
- Mixed-Signal Circuit Board Design for DSL Modem Board with OrCAD.
- ASIC RTL DSP PHY Design for DSL Modem chipset.
- Xilinx VirtexVI FPGA Design for communications IP Cores. ARM, Xilinx, AMBA/AHB, AXI, ModelSim.
- Xilinx FPGA RTL Design and lab bring-up for complex video chipset.
- Digital Circuit Board Design for complex video system.
- ASIC Consultant for ASIC co-simulation of SystemC to Verilog for an 802.11 Wireless Base-band Processor.
- Mixed-Signal (Analog / Digital) IC CMOS/BiCMOS Design engineer.
- Hardware engineer to provide analog / digital board design for complex networking equipment.
- Xilinx FPGA RTL review of control logic state machine and timing constraints. Client needed an independent review of another vendors design.
- ASIC/SoC Design Consultant for RTL Design from specification to tape-out including Synthesis and Timing for extremely complex graphics processor.
- ASIC/SoC Design Manager for extremely complex enterprise level SSD chipsets. Responsible to build team from ground up, define and direct overall design methodology, etc.
- FPGA design with Xilinx Virtex FPGA device for extremely complex networking chipset. Design included Micro-architecture, RTL Design, Synthesis, etc. Design included several high-speed interfaces such as: Xaui, QDR, DDR, RGMII, and Ethernet.
- Hardware engineering for complex high-speed board design of a small form-factor circuit board for wireless (Bluetooth), audio (AM/FM Tuner, Surround Sound, etc), and video technologies. Heavy exposure to Automotive Panel Link (Inova APIX), LVDS, digital RGB display encoding, and interfacing to LCD panels.
- ASIC RTL Design, Integration, Verification, Processor interconnect, and Static Timing Analysis for a “dual core” ARM9 WiMAX broadband SoC.
- FPGA Consultant to perform code analysis, debug, and redesign of existing blocks targeting a Xilinx VirtexV FPGA for a complex networking system which required a deep understanding of Packet Processing, Deep Packet Inspection, etc.
- FPGA Consultant to work closely with the ASIC team. Client wanted to test certain aspects of their design in an Altera Quartus II design, but lacked an understanding of Timing issues in the FPGA. We performed a design review and made appropriate timing changes in less than one month.
- Team of ASIC Verification engineers to perform both block and full-chip level functional verification of a NAND Flash Memory USB Stick device using SystemVerilog OVM.
- Four (4) Engineers provided to client for Xilinx VirtexV FPGA Verifcation for large network storage chip with high-speed I/O’s such as PCI Express, DDR2/3 memory controllers, using Verilog, SystemVerilog, AVM (Questa) and C.
- Board Design Consultant to develop x86 server mother board for a network server. PCI-Express, DDR2/3 memory controller interface, Signal Integrity.
- Five (5) ASIC Verification engineers for wireless start-up. Responsible for test bench development and implementation. FPGA lab bring-up and debug. SystemVerilog and custom UVM like methodology.
- Hardware board design (analog / digital) for complex and expensive milling/machining equipment.
- Five (5) Manufacturing Tools Design Engineers for aerospace manufacturing company. Heavy use of CATIA CAD tools. Computer Aided Design (CAD) drafting systems such as Catia V5, Catia V4, Autocad Mechanical Desktop or Solidworks and the creation of detailed assembly and component engineering drawings.
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