ASICSoft’s verification consulting division has extensive knowledge and experience with ASIC, SoC, and
FPGA verification projects. We can assist with early stage specification/architecture and implementation.

 

Expertise:

• Verification Architecture
• Test Bench Development
• Test Plan Development
• Bus Functional Models
• SystemVerilog (OVM, VMM, AVM)
• Verilog/VHDL
• Vera, Specman e, SystemC, C/C++, Perl, etc.
• I/O: Ethernet (10/100/1000), Xaui, DDR, QDR, PCIe, PCIx, SerDes, USB, AMBA, SDIO, etc.

 

 

Our Consulting Models:

Independent Consultants:

• When you need just one or maybe a few strong engineers to augment a project, having ASICSoft as
  your partner provides you with peace of mind knowing you’ll have your project moving ahead and
  hitting important milestones.
• ASICSoft’s vast network of design & verification engineers can work at your facility for the entire
  term of your project on a time & materials (hourly) basis.

 

Complete Verification Teams:


• At times you may need to a larger set of verification engineers to handle peaks in verification for com-
  plex chipsets. ASICSoft provides you peace of mind allowing you to scale your team quickly with
  teams as large as 5, 10, 15 or more verification engineers.
  
  
  

  This model can be delivered in two formats:

  • Complete outsourcing in our off-shore facility.
  • A combination of on-site/off-site. We provide one or two engineers to work on-site at your facility
    with the bulk of the team off-site. This way you have a face-to-face working relationship with a team leader who assists in managing your offshore resources.

 

• ASIC Consultant for ASIC co-simulation of SystemC to Verilog for an 802.11 Wireless Base-band Processor.
• Top-Level (full systems level) ASIC Design for complex ARM SoC 802.11 wireless base-band modem chip.
• ASIC/SoC Verification and Verification architecture using SystemVerilog VMM.
• Xilinx Virtex IV FPGA Design/Verification of PCI Express DDR2 memory controller for network storage device.
• ASIC Verification for Ethernet MAC portion of a complex switch/router using Vera.
• ASIC Verification of an ARC SoC audio multimedia chip.
• CPU Logic Verification with MIPS core using Verilog, C, and Assembly.
• ASIC RTL Design, Integration, Verification, Processor interconnect, and Static Timing Analysis for a “dual core” ARM9 WiMAX broadband SoC.
• Xilinx VirtexV FPGA Verifcation for large network storage chip with high-speed I/O’s such as PCI Express, DDR2/3 memory controllers, using Verilog, SystemVerilog, AVM (Questa) and C.
• Lead Verification effort for a complex multi-FPGA (Xilinx VirtexV) networking system using SystemVerilog
• ASIC Verification of custom IP blocks with Specman “e” and vManager for trimedia processor.
• ASIC Verification for complex C/C++ models for network server chipset. Drawing data from PCI-Express Transport Layer Protocol (TLP) into DMA and DDR2 controller.
• Block level design verification for a networking SoC. Verification environment is SystemVerilog VMM and Perl.
• ASIC Verification for both block and full-chip level functional verification of a NAND Flash Memory USB Stick device using SystemVerilog OVM.

 

OVM, UVM and SystemVerilog logos are registered trademarks of their respective companies/organizations

 

 

 

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