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Description |
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 Active-HDL |
Active-HDL is an integrated easy-to-use FPGA Design and Simulation solution, providing a robust design creation tool suite, a high-performance mixed-language simulator and a multi-vendor FPGA flow manager that controls Simulation, Synthesis and Implementation for industry leading FPGA devices, such as Actel™, Altera®, Lattice®, Quicklogic®, Xilinx® and over 87 popular EDA tools, all-in-one common environment.
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Riviera-PRO™ is a high-performance verification platform for ASIC and FPGA design teams, equipped with mixed-language simulation engine and advanced debugging tools. Riviera-PRO supports Electronic System Level (ESL) Verification with SystemC and SystemVerilog, Assertions Based Verification (ABV), Transaction Level Modeling (TLM) and VHDL/Verilog Design Rule Checking. Riviera-PRO works in command line mode for maximum speed and provides a powerful GUI for enhanced editing, tracing, and debugging. Riviera-PRO interfaces to popular EDA products, such as Synopsys® SmartModels™, SpringSoft®, Denali®, MATLAB® and Simulink®.
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ALINT™ is an RTL design analysis tool that identifies design issues early in the development cycle. VHDL, Verilog® or mixed-language designs are checked for coding inconsistencies, design structure issues, synthesis, simulation, and clock and reset issues prior to simulation and synthesis. ALINT significantly reduces verification time for complex FPGA and ASIC designs, results in uniform, reusable and reliable code and reduces the risk of costly ASIC re-spins. Comprehensive rule sets are available for VHDL, Verilog and mixed-language designs. ALINT includes powerful utilities for rule management, violation analysis, and debugging. |
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